The documents for this chipset are only available under NDA, so I have never seen them. This page explains what I have worked out from the Linux source code.
For some inexplicable reason this chipset doesn't use the normal semantics for the PCI cache line size register (offset 0xc in PCI configuration space). Instead of actually setting this to the cache line size, you set it to a magic number. This magic number is 255 for revision zero, and 1 for all other revisions.
The SCSC register is a 1 byte register found at offset 0x8A is the PCI configuration space
Bits 5 and 6 of the SCSC (no idea what that actually stands for) are used to set the ATA bus clocking mode.
| Value of bits 5,6 | Function |
|---|---|
| 0 | Run at 100Mhz |
| 1 | Run at 133Mhz |
| 2 | Run at 2x PCI |
| 3 | Disabled |
Bit 0 indicates if there BAR 5 is enabled. If so it means that the chip functionality can be accessed through memspace access rather than configuration and I/O space. I don't know how this memory area is laid out, however it could be figured out from the Linux driver.
There is one register for the primary and secondary channel found at 0x80 and 0x84 in the PCI configuration space. Both registers are 1 byte wide.
Bits 0-2 are used for the master driver and bits 4-6 for the slave drive.
| Value of Mode | Function |
|---|---|
| 0 | Run at 100Mhz |
| 1 | PIO |
| 2 | MDMA |
| 3 | UDMA |
The MDMA register is sixteen bytes byte, and there is one for each driver:
| Drive | Offset in PCI config space |
|---|---|
| Primary Master (0) | 0xA4 |
| Primary Slave (1) | 0xA6 |
| Secondary Master (2) | 0xB4 |
| Secondary Slave (3) | 0xB6 |
I don't know the semantics of the bits, however there is a magic number that must be set depending on which MDMA mode you are in:
| MDMA mode | Value |
|---|---|
| Mode 0 | 0x2208 |
| Mode 1 | 0x10C2 |
| Mode 2 | 0x10C1 |
The UDMA register is sixteen bytes byte, and there is one for each driver:
| Drive | Offset in PCI config space |
|---|---|
| Primary Master (0) | 0xAC |
| Primary Slave (1) | 0xAE |
| Secondary Master (2) | 0xBC |
| Secondary Slave (3) | 0xBE |
I don't know the semantics of the bits, however there is a magic depending on which mode you are in. Only the bottom 6 bits should be changed (I don't know why), and we only ever change the bottom four bits. Again there is a magic number based on what UDMA mode you are in and what clocking mode you have set (see above).
| UDMA mode | Value (100Mhz) | Value (133Mhz) |
|---|---|---|
| Mode 0 | 0xC | 0xF |
| Mode 1 | 0x7 | 0xB |
| Mode 2 | 0x5 | 0x7 |
| Mode 3 | 0x4 | 0x5 |
| Mode 4 | 0x2 | 0x3 |
| Mode 5 | 0x1 | 0x2 |
| Mode 6 | N/A | 0x1 |
There are other magic registers for setting up PIO timing, but as I have never need to use PIO I haven't tried to find out the exact semantics of them.