Sil680 IDE Chipset Documentation

The documents for this chipset are only available under NDA, so I have never seen them. This page explains what I have worked out from the Linux source code.

PCI cache line size

For some inexplicable reason this chipset doesn't use the normal semantics for the PCI cache line size register (offset 0xc in PCI configuration space). Instead of actually setting this to the cache line size, you set it to a magic number. This magic number is 255 for revision zero, and 1 for all other revisions.

SCSC register

The SCSC register is a 1 byte register found at offset 0x8A is the PCI configuration space

Bits 5 and 6 of the SCSC (no idea what that actually stands for) are used to set the ATA bus clocking mode.

Value of bits 5,6Function
0Run at 100Mhz
1Run at 133Mhz
2Run at 2x PCI
3Disabled

Bit 0 indicates if there BAR 5 is enabled. If so it means that the chip functionality can be accessed through memspace access rather than configuration and I/O space. I don't know how this memory area is laid out, however it could be figured out from the Linux driver.

Mode register

There is one register for the primary and secondary channel found at 0x80 and 0x84 in the PCI configuration space. Both registers are 1 byte wide.

Bits 0-2 are used for the master driver and bits 4-6 for the slave drive.

Value of ModeFunction
0Run at 100Mhz
1PIO
2MDMA
3UDMA

MDMA timing register

The MDMA register is sixteen bytes byte, and there is one for each driver:

DriveOffset in PCI config space
Primary Master (0)0xA4
Primary Slave (1)0xA6
Secondary Master (2)0xB4
Secondary Slave (3)0xB6

I don't know the semantics of the bits, however there is a magic number that must be set depending on which MDMA mode you are in:

MDMA modeValue
Mode 00x2208
Mode 10x10C2
Mode 20x10C1

UDMA timing register

The UDMA register is sixteen bytes byte, and there is one for each driver:

DriveOffset in PCI config space
Primary Master (0)0xAC
Primary Slave (1)0xAE
Secondary Master (2)0xBC
Secondary Slave (3)0xBE

I don't know the semantics of the bits, however there is a magic depending on which mode you are in. Only the bottom 6 bits should be changed (I don't know why), and we only ever change the bottom four bits. Again there is a magic number based on what UDMA mode you are in and what clocking mode you have set (see above).

UDMA modeValue (100Mhz)Value (133Mhz)
Mode 00xC0xF
Mode 10x70xB
Mode 20x50x7
Mode 30x40x5
Mode 40x20x3
Mode 50x10x2
Mode 6N/A0x1

PIO timing registers

There are other magic registers for setting up PIO timing, but as I have never need to use PIO I haven't tried to find out the exact semantics of them.